1. Field of the Invention
The present invention relates generally to a semiconductor device and a manufacturing method thereof, and particularly to a field effect transistor that has a high drain breakdown voltage during operation.
2. Description of the Related Art
In an electronic apparatus such as a laptop computer or a digital video camera, plural Li-ion rechargeable batteries that are serially connected may be used as a power source. Such an electronic apparatus may use a power source IC as a power source circuit for charging the Li-ion rechargeable battery and a power source circuit for supplying power to the electronic apparatus while charging the Li-ion rechargeable battery. In comparison with a regular logic IC, the power source IC uses a relatively high power supply voltage of around a dozen to several dozen volts. Also, in the power source IC, high integration of numerous circuits including power source circuits and power control logic circuits is demanded, and in turn, plural power supply voltages may be used within one IC chip, for example.
When a transistor such as a MOS transistor that is integrated in the power source IC is in operation, a drain breakdown voltage that is greater than the power supply voltage may be required, and when the drain breakdown voltage is insufficient, the power IC may overheat and the power consumption may be increased. In the prior art, measures are taken with respect to the circuit for securing a sufficient breakdown voltage; namely, a multiple connection of MOS transistors is realized. However, in such a case a large number of MOS transistors are required, this being an obstacle to reducing the area of the IC chip (i.e., miniaturization of the IC chip).
In turn, in recent years and continuing, measures that are addressed to the MOS transistor itself are being developed for increasing the drain breakdown voltage. For example, a high breakdown voltage MOS transistor is being used such as an offset MOS transistor having a drain electrode and a gate electrode that are set apart from one another via an offset region with a low impurity concentration, or a LD (Laterally Diffused) MOS transistor having a drain electrode and a gate electrode that are set apart from one another via a field oxide layer. In such high breakdown voltage MOS transistors, a drain region portion that comes into contact with the drain electrode forms an impurity diffused region with a higher concentration of impurities compared to the rest of the drain region so that the contact resistance may be decreased at the contact region.
However, in a case where a MOS transistor is arranged to include a first drain region having a relatively low impurity concentration and extending from a region directly below the gate electrode to a region in contact with the drain electrode, and a contact region within the first drain region to come into contact with the drain electrode and having a higher impurity concentration compared to the first drain region, bipolar action may easily occur and the drain breakdown voltage may be decreased. It is noted that bipolar action refers to a sudden increase in the drain current as a result of an avalanche breakdown that occurs when a high voltage is simultaneously applied to the drain and the gate.
In turn, a MOS transistor as is shown in FIG.1 that is arranged to prevent the generation of bipolar action is disclosed in Japanese Laid-Open Patent Publication No. 2002-124671. The MOS transistor 100 of FIG. 1 includes a first drain region 102 that extends from a region directly below an end portion of a gate electrode 101 and below a high concentration drain region 102, and a second drain region 104 that is formed within the first drain region 103 and is arranged to have a higher impurity concentration compared to the first drain region 103.
However, in the example of FIG. 1, the first drain region 103 as well as the second drain region 104 are arranged to extend over a region directly below the gate electrode 101. In such a case, when a high voltage is applied to the high concentration drain region 102, a short channel effect may easily occur. It is noted that the short channel effect may be prevented by securing a sufficient gate length; however, this leads to enlargement of the device area to thereby hamper miniaturization of the IC chip.
Also, in a case where the second drain region 104 is not provided, since the high concentration drain region 102 has a high concentration of impurities, a depletion layer generated between the first drain region 103 and the substrate 105 may be prevented from being diffused toward the first drain region 103. Thereby, sufficient field dispersion may not be realized in the region, and as a result, the drain breakdown voltage during operation may be decreased.